VHDL program to implement NOT gate using data flow modeling.

--VHDL program to implement NOT gate using data flow modeling.

library IEEE;

use IEEE.std_logic_1164.all;

entity not_gate is

port(

I1 : in std_logic;

OA : out std_logic);

end entity not_gate;

architecture behav of not_gate is

begin

OA <= not I1;

end architecture behav;

For Safe Downloading of ModelSim (32/64 bit) please visit :-

https://bit.ly/3thv8Oh

For Safe Downloading of this program file please visit :-

http://bit.ly/3ap3pml