Program for 2:4 decoder using VHDL Data flow modeling.

--Program for 2 to 4 decoder using VHDL Data flow modeling.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder_2_4 is

Port ( S : in STD_LOGIC_VECTOR (1 downto 0);

Q : out STD_LOGIC_VECTOR (3 downto 0));

end decoder_2_4;

architecture dataflow of decoder_2_4 is

begin

Q <= "0001" when S="00"

else"0010" when S="01"

else"0100" when S="10"

else"1000" when S="11";

end dataflow;

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