VHDL Program to implement 2:4 Decoder using If-Else statement.

--VHDL Program to implement 2 to 4 Decoder using If-Else statement.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity decoder1 is

port(

a : in STD_LOGIC_VECTOR(1 downto 0);

b : out STD_LOGIC_VECTOR(3 downto 0)

);

end decoder1;

architecture bhv of decoder1 is

begin

process(a)

begin

if (a="00") then

b <= "0001";

elsif (a="01") then

b <= "0010";

elsif (a="10") then

b <= "0100";

else

b <= "1000";

end if;

end process;

end bhv;

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