VHDL program for implementing a 8:1 multiplexer using if-else statements.

--VHDL program for implementing a 8 to 1 multiplexer using if-else statements.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity multiplexer8_1_if_else is

     port(

         din : in STD_LOGIC_VECTOR(7 downto 0);

         sel : in STD_LOGIC_VECTOR(2 downto 0);

         dout : out STD_LOGIC

         );

end multiplexer8_1_if_else;

architecture multiplexer8_1_arc of multiplexer8_1_if_else is

begin

    dout <= din(7) when (sel="000") else

            din(6) when (sel="001") else

            din(5) when (sel="010") else

            din(4) when (sel="011") else

            din(3) when (sel="100") else

            din(2) when (sel="101") else

            din(1) when (sel="110") else

            din(0);

end multiplexer8_1_arc;

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VHDL Program to implement Priority Encoder using If-Else statement.

--VHDL Program to implement Priority Encoder using If-Else statement.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity encoder1 is

port(

a : in STD_LOGIC_VECTOR(3 downto 0);

b : out STD_LOGIC_VECTOR(1 downto 0)

);

end encoder1;

architecture bhv of encoder1 is

begin

process(a)

begin

if (a="1000") then

b <= "00";

elsif (a="0100") then

b <= "01";

elsif (a="0010") then

b <= "10";

elsif (a="0001") then

b <= "11";

else

b <= "ZZ";

end if;

end process;

end bhv;

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VHDL Program to implement 2:4 Decoder using If-Else statement.

--VHDL Program to implement 2 to 4 Decoder using If-Else statement.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity decoder1 is

port(

a : in STD_LOGIC_VECTOR(1 downto 0);

b : out STD_LOGIC_VECTOR(3 downto 0)

);

end decoder1;

architecture bhv of decoder1 is

begin

process(a)

begin

if (a="00") then

b <= "0001";

elsif (a="01") then

b <= "0010";

elsif (a="10") then

b <= "0100";

else

b <= "1000";

end if;

end process;

end bhv;

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VHDL Program to implement 1:4 DeMultiplexer using If-Else statement.

--VHDL Program to implement 1 to 4 DeMultiplexer using If-Else statement.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity demultiplexer1_4 is

port(

din : in STD_LOGIC;

sel : in STD_LOGIC_VECTOR(1 downto 0);

dout : out STD_LOGIC_VECTOR (3 downto 0)

);

end demultiplexer1_4;

architecture demultiplexer1_4_arc of demultiplexer1_4 is

begin

demux : process (din,sel) is

begin

if (sel="00") then

dout <= din & "000";

elsif (sel="01") then

dout <= '0' & din & "00";

elsif (sel="10") then

dout <= "00" & din & '0';

else

dout <= "000" & din;

end if;

end process demux;

end demultiplexer1_4_arc;

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VHDL Program to implement 4:1 Multiplexer using If-Else statement

--VHDL Program to implement 4 to 1 Multiplexer using If-Else statement

library IEEE; 

use IEEE.STD_LOGIC_1164.all; 

entity multiplexer_4_1 is port( din : in STD_LOGIC_VECTOR(3 downto 0);

sel : in STD_LOGIC_VECTOR(1 downto 0); 

dout : out STD_LOGIC ); 

end multiplexer_4_1; 

architecture multiplexer4_1_arc of multiplexer_4_1 is begin mux : 

process (din,sel) is begin if (sel="00") then dout <= din(3); 

elsif (sel="01") then dout <= din(2); 

elsif (sel="10") then dout <= din(1); 

else dout <= din(0); 

end if; 

end process mux;

end multiplexer4_1_arc;

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