VHDL program for implementing the following SOP expression using data flow modelling (a ^ b) v (b ^ ~c) v (c ^ ~a)

--VHDL program for implementing the following SOP expression using data flow modelling:
--(a ^ b) v (b ^ ~c) v (c ^ ~a)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity sum_of_product15 is

Port

(A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

F : out STD_LOGIC);

end sum_of_product15;

architecture gate_level of sum_of_product15 is

begin

F <= ((A AND B)OR(B AND (NOT C))OR(C AND (NOT A)));

end gate_level;

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