Program to create a parity checker circuit in VHDL Modelling.

--Program to create a parity checker circuit in VHDL Modelling.

library IEEE;

use IEEE.std_logic_1164.all;

entity parity_checker is

port ( IE : in std_logic; -- Even input IE active high

IO : in std_logic; -- Odd input IO active high

OE : out std_logic; -- Even output OE active high

OO : out std_logic; -- Odd output OO active high

D : in std_logic_vector(3 downto 0));

end parity_checker;

architecture parity_arch of parity_checker is

signal TEMP : std_logic;

begin

TEMP <= D(0) xor D(1) xor D(2) xor D(3);

OE <= TEMP xor IE;

OO <= TEMP xor IO;

end parity_arch;

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