Program to create 1:4 Demultiplexer using VHDL.

--Program to create 1 to 4 Demultiplexer using VHDL.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity demux_1_4 is

port(

din : in STD_LOGIC;

sel : in STD_LOGIC_VECTOR(1 downto 0);

dout : out STD_LOGIC_VECTOR(3 downto 0)

);

end demux_1_4;

architecture demultiplexer_case_arc of demux_1_4 is

begin

demux : process (din,sel) is

begin

case sel is

when "00" => dout <= din & "000";

when "01" => dout <= '0' & din & "00";

when "10" => dout <= "00" & din & '0';

when others => dout <= "000" & din;

end case;

end process demux;

end demultiplexer_case_arc;

For Safe Downloading of ModelSim (32/64 bit) please visit :-

https://bit.ly/3thv8Oh

For Safe Downloading of this program file please visit :-

http://bit.ly/3pIVNkS