Program for 8:1 encoder using VHDL behavioral modeling.
--Program for 8 to 1 encoder using VHDL behavioral modeling.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY behav_encoder_8_1 IS
PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DOUT:OUT STD_LOGIC);
END behav_encoder_8_1;
ARCHITECTURE BEHAVIORAL OF behav_encoder_8_1 IS
BEGIN
PROCESS(DIN,SEL)
BEGIN
CASE SEL IS
WHEN"000"=>DOUT<=DIN(0);
WHEN"001"=>DOUT<=DIN(1);
WHEN"010"=>DOUT<=DIN(2);
WHEN"011"=>DOUT<=DIN(3);
WHEN"100"=>DOUT<=DIN(4);
WHEN"101"=>DOUT<=DIN(5);
WHEN"110"=>DOUT<=DIN(6);
WHEN"111"=>DOUT<=DIN(7);
WHEN OTHERS=>
DOUT<='Z';
END CASE;
END PROCESS;
END BEHAVIORAL;
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Labels: 8:1 encoder, Behavioral Modeling, Model Sim, program, VHDL
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