Program for 3:8 decoder using VHDL Data flow modeling.
--Program for 3 to 8 decoder using VHDL Data flow modeling.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_3_8 is
Port ( S : in STD_LOGIC_VECTOR (2 downto 0);
Q : out STD_LOGIC_VECTOR (7 downto 0));
end decoder_3_8;
architecture dataflow of decoder_3_8 is
begin
Q <="00000001" when S="000" else
"00000010" when S="001" else
"00000100" when S="010" else
"00001000" when S="011" else
"00010000" when S="100" else
"00100000" when S="101" else
"01000000" when S="110" else
"10000000";
end dataflow;
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Labels: 3:8 decoder, Model Sim, program, VHDL
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