Program for 8:3 Encoder using VHDL data flow modeling.

--Program for 8 to 3 Encoder using VHDL data flow modeling.

library ieee;

use ieee.std_logic_1164.all;

entity data_flow_encoder_8_3 is

port(i0,i1,i2,i3,i4,i5,i6,i7:in bit; o0,o1,o2: out bit);

end data_flow_encoder_8_3;

architecture dataflow of data_flow_encoder_8_3 is

begin

o0<=i4 or i5 or i6 or i7;

o1<=i2 or i3 or i6 or i7;

o2<=i1 or i3 or i5 or i7;

end dataflow;

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