Program to create a parity generator circuit in VHDL Modelling.

--Program to create a parity generator circuit in VHDL Modelling.

library ieee;

use ieee.std_logic_1164.all;

entity parity_generator is

port (a0, a1, a2, a3: in std_logic; p_odd, p_even: out std_logic);

end parity_generator;

architecture parity of parity_generator is

begin

process (a0, a1, a2, a3)

begin

if (a0 ='0' and a1 ='0' and a2 ='0' and a3 ='0')

then p_odd <= '0';

p_even <= '0';

else

p_odd <= (((a0 xor a1) xor a2) xor a3);

p_even <= not(((a0 xor a1) xor a2) xor a3);

end if;

end process;

end parity;

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