Program to create Full Subtractor using VHDL behavioral modelling

--Program to create Full Subtractor using VHDL behavioral modelling.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_subtractor_behav is

Port ( a : in std_logic;

b : in std_logic;

c : in std_logic;

d : out std_logic;

di : out std_logic);

end full_subtractor_behav;

architecture Behavioral of full_subtractor_behav is

begin

process(a,b,c)

begin

if(a='0' and b='0' and c='0')then

d<='0';

di<='0';

elsif( a='0' and b='0' and c='1')then

d<='1';

di<='1';

elsif( a='0' and b='1' and c='0')then

d<='1';

di<='1';

elsif( a='0' and b='1' and c='1')then

d<='0';

di<='1';

elsif( a='1' and b='0' and c='0')then

d<='1';

di<='0';

elsif( a='1' and b='0' and c='1')then

d<='0';

di<='0';

elsif( a='1' and b='1' and c='0')then

d<='0';

di<='0';

else

d<='1';

di<='1';

end if;

end process;

end Behavioral;

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