VHDL Code to implement 128X8 single port RAM.

--VHDL Code to implement 128X8 single port RAM.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USE ieee.numeric_std.ALL;

entity Single_port_RAM_VHDL is

port(

RAM_ADDR: in std_logic_vector(6 downto 0);

RAM_DATA_IN: in std_logic_vector(7 downto 0);

RAM_WR: in std_logic;

RAM_CLOCK: in std_logic;

RAM_DATA_OUT: out std_logic_vector(7 downto 0)

);

end Single_port_RAM_VHDL;

architecture Behavioral of Single_port_RAM_VHDL is

type RAM_ARRAY is array (0 to 127 ) of std_logic_vector (7 downto 0);

signal RAM: RAM_ARRAY :=(

x"55",x"66",x"77",x"67",-- 0x00:

x"99",x"00",x"00",x"11",-- 0x04:

x"00",x"00",x"00",x"00",-- 0x08:

x"00",x"00",x"00",x"00",-- 0x0C:

x"00",x"00",x"00",x"00",-- 0x10:

x"00",x"00",x"00",x"00",-- 0x14:

x"00",x"00",x"00",x"00",-- 0x18:

x"00",x"00",x"00",x"00",-- 0x1C:

x"00",x"00",x"00",x"00",-- 0x20:

x"00",x"00",x"00",x"00",-- 0x24:

x"00",x"00",x"00",x"00",-- 0x28:

x"00",x"00",x"00",x"00",-- 0x2C:

x"00",x"00",x"00",x"00",-- 0x30:

x"00",x"00",x"00",x"00",-- 0x34:

x"00",x"00",x"00",x"00",-- 0x38:

x"00",x"00",x"00",x"00",-- 0x3C:

x"00",x"00",x"00",x"00",-- 0x40:

x"00",x"00",x"00",x"00",-- 0x44:

x"00",x"00",x"00",x"00",-- 0x48:

x"00",x"00",x"00",x"00",-- 0x4C:

x"00",x"00",x"00",x"00",-- 0x50:

x"00",x"00",x"00",x"00",-- 0x54:

x"00",x"00",x"00",x"00",-- 0x58:

x"00",x"00",x"00",x"00",-- 0x5C:

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00"

);

begin

process(RAM_CLOCK)

begin

if(rising_edge(RAM_CLOCK)) then

if(RAM_WR='1') then

RAM(to_integer(unsigned(RAM_ADDR))) <= RAM_DATA_IN;

end if;

end if;

end process;

RAM_DATA_OUT <= RAM(to_integer(unsigned(RAM_ADDR)));

end Behavioral;

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