VHDL program for implementing a 3:8 decoder using behavioural modelling.

--VHDL program for implementing a 3 to 8 decoder using behavioural modelling.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY decoder_3_8_behav IS

PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);

SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);

DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END decoder_3_8_behav;

ARCHITECTURE BEHAVIORAL OF decoder_3_8_behav IS

BEGIN

PROCESS(SEL,DIN)

BEGIN

CASE SEL IS

WHEN "000"=>DOUT<="00000001";

WHEN "001"=>DOUT<="00000010";

WHEN "010"=>DOUT<="00000100";

WHEN "011"=>DOUT<="00001000";

WHEN "100"=>DOUT<="00010000";

WHEN "101"=>DOUT<="00100000";

WHEN "110"=>DOUT<="01000000";

WHEN "111"=>DOUT<="10000000";

WHEN OTHERS=>DOUT<="ZZZZZZZZ";

END CASE;

END PROCESS;

END BEHAVIORAL;

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