VHDL Code to implement RAM by INTEL.

--VHDL Code to implement RAM by INTEL.

library IEEE;

use IEEE.std_logic_1164.all;

entity ram_intel is

port(

clock : in std_logic;

data : in std_logic_vector(3 downto 0);

write_addr : in integer range 0 to 31;

read_addr : in integer range 0 to 31;

we : in std_logic;

q : out std_logic_vector(3 downto 0)

);

end ram_intel;

architecture rtl of ram_intel is

type mem is array(0 to 31) of std_logic_vector(3 downto 0);

signal ram_block : mem;

begin

process(clock)

begin

if (clock'event and clock='1')then

if(we = '1')then

ram_block(write_addr)<=data;

end if;

q<=ram_block(read_addr);

end if;

end process;

end rtl;

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