VHDL program for implementing the following POS expression using data flow modelling: (~a v~ b) ^ (~a v c) ^ (b v c)

--VHDL program for implementing the following POS expression using data flow modelling:
--(~a v~ b) ^ (~a v c) ^ (b v c)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity product_of_sum6 is

Port

(A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

F : out STD_LOGIC);

end product_of_sum6;

architecture gate_level of product_of_sum6 is

begin

F <= (((NOT A)OR(NOT B))AND((NOT A)OR C)AND(B OR C));

end gate_level;

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