VHDL Program to implement 2:4 Decoder using Case statement.

--VHDL Program to implement 2 to 4 Decoder using Case statement.

library IEEE; 

use IEEE.STD_LOGIC_1164.all; 

entity decoder_case is port( din : in STD_LOGIC_VECTOR(1 downto 0); 

dout : out STD_LOGIC_VECTOR(3 downto 0) ); 

end decoder_case; 

architecture decoder_case_arc of decoder_case is begin decoder : 

process (din) is begin case din is when "00" => dout <= "1000"; 

when "01" => dout <= "0100"; 

when "10" => dout <= "0010"; 

when others => dout <= "0001"; 

end case; 

end process decoder; 

end decoder_case_arc;

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Program for 2:4 decoder using VHDL Data flow modeling.

--Program for 2 to 4 decoder using VHDL Data flow modeling.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder_2_4 is

Port ( S : in STD_LOGIC_VECTOR (1 downto 0);

Q : out STD_LOGIC_VECTOR (3 downto 0));

end decoder_2_4;

architecture dataflow of decoder_2_4 is

begin

Q <= "0001" when S="00"

else"0010" when S="01"

else"0100" when S="10"

else"1000" when S="11";

end dataflow;

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VHDL Program to implement 2:4 Decoder using If-Else statement.

--VHDL Program to implement 2 to 4 Decoder using If-Else statement.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity decoder1 is

port(

a : in STD_LOGIC_VECTOR(1 downto 0);

b : out STD_LOGIC_VECTOR(3 downto 0)

);

end decoder1;

architecture bhv of decoder1 is

begin

process(a)

begin

if (a="00") then

b <= "0001";

elsif (a="01") then

b <= "0010";

elsif (a="10") then

b <= "0100";

else

b <= "1000";

end if;

end process;

end bhv;

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