VHDL program to implement any Boolean expression of POS for using VHDL data flow modeling

--VHDL program to implement any Boolean expression of POS for using VHDL data flow modeling.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity product_of_sum is

Port

(A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

F : out STD_LOGIC);

end product_of_sum;

architecture gate_level of product_of_sum is

begin

F <= ((A OR B OR C)AND((NOT A)OR B OR C )AND((NOT A)OR(NOT B) OR C)AND((NOT A)OR(NOT B)OR(NOT C)));

end gate_level;

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