VHDL program to implement any Boolean expression of SOP form using VHDL data flow modeling.

--VHDL program to implement any Boolean expression of SOP form using VHDL data flow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sum_of_product is
Port
(A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
F : out STD_LOGIC);
end sum_of_product;
architecture gate_level of sum_of_product is
begin
F <= (((NOT A) AND (NOT B) AND (C )) OR ((NOT A) AND (B) AND (NOT C)) OR ((NOT A) AND B AND C) OR(A AND (NOT B) AND C));
end gate_level;

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