VHDL program to implement NOR gate using data flow modeling.

--VHDL program to implement NOR gate using data flow modeling.

library IEEE;

use IEEE.std_logic_1164.all;

entity nor_gate is

port(

I1 : in std_logic;

I2 : in std_logic;

OA : out std_logic);

end entity nor_gate;

architecture behav of nor_gate is

begin

OA <= I1 nor I2;

end architecture behav;

For Safe Downloading of ModelSim (32/64 bit) please visit :-

https://bit.ly/3thv8Oh

For Safe Downloading of this program file please visit :-

http://bit.ly/36DI0oq