VHDL program to implement NAND gate using data flow modeling.

--VHDL program to implement NAND gate using data flow modeling.

library IEEE;
use IEEE.std_logic_1164.all;
entity nand_gate is
port(
I1 : in std_logic;
I2 : in std_logic;
OA : out std_logic);
end entity nand_gate;
architecture behav of nand_gate is
begin
OA <= I1 nand I2;
end architecture behav;

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