VHDL program to implement Half Subtractor using data flow modeling.

--VHDL program to implement Half Subtractor using data flow modeling.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity half_sub is

port( A, B : in std_logic;

DIFF, Borrow : out std_logic);

end entity;

architecture dataflow of half_sub is

begin

DIFF <= A xor B;

Borrow <= (not A) and B;

end architecture;

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