VHDL program for implementing the following POS expression using data flow modelling: (~a v~ b) ^ (~a v c) ^ (b v c)

--VHDL program for implementing the following POS expression using data flow modelling:
--(~a v~ b) ^ (~a v c) ^ (b v c)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity product_of_sum6 is

Port

(A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

F : out STD_LOGIC);

end product_of_sum6;

architecture gate_level of product_of_sum6 is

begin

F <= (((NOT A)OR(NOT B))AND((NOT A)OR C)AND(B OR C));

end gate_level;

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VHDL program for implementing the following SOP expression using data flow modelling (a ^ b) v (b ^ ~c) v (c ^ ~a)

--VHDL program for implementing the following SOP expression using data flow modelling:
--(a ^ b) v (b ^ ~c) v (c ^ ~a)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity sum_of_product15 is

Port

(A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

F : out STD_LOGIC);

end sum_of_product15;

architecture gate_level of sum_of_product15 is

begin

F <= ((A AND B)OR(B AND (NOT C))OR(C AND (NOT A)));

end gate_level;

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VHDL program for implementing a 8:1 multiplexer using if-else statements.

--VHDL program for implementing a 8 to 1 multiplexer using if-else statements.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity multiplexer8_1_if_else is

     port(

         din : in STD_LOGIC_VECTOR(7 downto 0);

         sel : in STD_LOGIC_VECTOR(2 downto 0);

         dout : out STD_LOGIC

         );

end multiplexer8_1_if_else;

architecture multiplexer8_1_arc of multiplexer8_1_if_else is

begin

    dout <= din(7) when (sel="000") else

            din(6) when (sel="001") else

            din(5) when (sel="010") else

            din(4) when (sel="011") else

            din(3) when (sel="100") else

            din(2) when (sel="101") else

            din(1) when (sel="110") else

            din(0);

end multiplexer8_1_arc;

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VHDL program for implementing a 3:8 decoder using behavioural modelling.

--VHDL program for implementing a 3 to 8 decoder using behavioural modelling.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY decoder_3_8_behav IS

PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);

SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);

DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END decoder_3_8_behav;

ARCHITECTURE BEHAVIORAL OF decoder_3_8_behav IS

BEGIN

PROCESS(SEL,DIN)

BEGIN

CASE SEL IS

WHEN "000"=>DOUT<="00000001";

WHEN "001"=>DOUT<="00000010";

WHEN "010"=>DOUT<="00000100";

WHEN "011"=>DOUT<="00001000";

WHEN "100"=>DOUT<="00010000";

WHEN "101"=>DOUT<="00100000";

WHEN "110"=>DOUT<="01000000";

WHEN "111"=>DOUT<="10000000";

WHEN OTHERS=>DOUT<="ZZZZZZZZ";

END CASE;

END PROCESS;

END BEHAVIORAL;

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VHDL program for implementing a 1:8 demultiplexer using Case statement.

--VHDL program for implementing a 1 to 8 demultiplexer using Case statement.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity demultiplexer1_8_case is

     port(

         din : in STD_LOGIC;

         sel : in STD_LOGIC_VECTOR(2 downto 0);

         dout : out STD_LOGIC_VECTOR(7 downto 0)

         );

end demultiplexer1_8_case;

architecture demultiplexer1_8_arc of demultiplexer1_8_case is

begin

    dout <= (din & "0000000") when (sel="000") else

            ('0' & din & "000000") when (sel="001") else

            ("00" & din & "00000") when (sel="010") else

            ("000" & din & "0000") when (sel="011") else

            ("0000" & din & "000") when (sel="100") else

            ("00000" & din & "00") when (sel="101") else

            ("000000" & din & '0') when (sel="110") else

            ("0000000" & din) ;

end demultiplexer1_8_arc;

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VHDL Code to design an ALU.

--VHDL Code to design an ALU.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity alu is

Port ( inp_a : in signed(3 downto 0);

inp_b : in signed(3 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

out_alu : out signed(3 downto 0));

end alu;

architecture Behavioral of alu is

begin

process(inp_a, inp_b, sel)

begin

case sel is

when "000" =>

out_alu<= inp_a + inp_b;

when "001" =>

out_alu<= inp_a - inp_b;

when "010" =>

out_alu<= inp_a - 1;

when "011" =>

out_alu<= inp_a + 1;

when "100" =>

out_alu<= inp_a and inp_b;

when "101" =>

out_alu<= inp_a or inp_b;

when "110" =>

out_alu<= not inp_a ;

when "111" =>

out_alu<= inp_a xor inp_b;

when others =>

NULL;

end case;

end process;

end Behavioral;

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VHDL Code to implement RAM by INTEL.

--VHDL Code to implement RAM by INTEL.

library IEEE;

use IEEE.std_logic_1164.all;

entity ram_intel is

port(

clock : in std_logic;

data : in std_logic_vector(3 downto 0);

write_addr : in integer range 0 to 31;

read_addr : in integer range 0 to 31;

we : in std_logic;

q : out std_logic_vector(3 downto 0)

);

end ram_intel;

architecture rtl of ram_intel is

type mem is array(0 to 31) of std_logic_vector(3 downto 0);

signal ram_block : mem;

begin

process(clock)

begin

if (clock'event and clock='1')then

if(we = '1')then

ram_block(write_addr)<=data;

end if;

q<=ram_block(read_addr);

end if;

end process;

end rtl;

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