Program to create Full Adder using case statement in VHDL behavioral modelling.

--Program to create Full Adder using case statement in VHDL behavioral modelling.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder_case is

Port ( a : in std_logic;

b : in std_logic;

c : in std_logic;

s : out std_logic;

cr : out std_logic);

end full_adder_case;

architecture Behavioral of full_adder_case is

begin

process(a,b,c)

begin

if(a='0' and b='0' and c='0')then

s<='0';

cr<='0';

elsif( a='0' and b='0' and c='1')then

s<='1';

cr<='0';

elsif( a='0' and b='1' and c='0')then

s<='1';

cr<='0';

elsif( a='0' and b='1' and c='1')then

s<='0';

cr<='1';

elsif( a='1' and b='0' and c='0')then

s<='1';

cr<='0';

elsif( a='1' and b='0' and c='1')then

s<='0';

cr<='1';

elsif( a='1' and b='1' and c='0')then

s<='0';

cr<='1';

else

s<='1';

cr<='1';

end if;

end process;

end Behavioral;

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Program to create Full Adder using VHDL behavioral modelling.

--Program to create Full Adder using VHDL behavioral modelling.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder_behav is

Port ( a : in std_logic;

b : in std_logic;

c : in std_logic;

s : out std_logic;

cr : out std_logic);

end full_adder_behav;

architecture Behavioral of full_adder_behav is

begin

process(a,b,c)

begin

if(a='0' and b='0' and c='0')then

s<='0';

cr<='0';

elsif( a='0' and b='0' and c='1')then

s<='1';

cr<='0';

elsif( a='0' and b='1' and c='0')then

s<='1';

cr<='0';

elsif( a='0' and b='1' and c='1')then

s<='0';

cr<='1';

elsif( a='1' and b='0' and c='0')then

s<='1';

cr<='0';

elsif( a='1' and b='0' and c='1')then

s<='0';

cr<='1';

elsif( a='1' and b='1' and c='0')then

s<='0';

cr<='1';

else

s<='1';

cr<='1';

end if;

end process;

end Behavioral;

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VHDL program to implement Full Adder using data flow modeling.

--VHDL program to implement Full Adder using data flow modeling.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity full_adder_vhdl_code is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Cin : in STD_LOGIC;

S : out STD_LOGIC;

Cout : out STD_LOGIC);

end full_adder_vhdl_code;

architecture gate_level of full_adder_vhdl_code is

begin

S <= A XOR B XOR Cin ;

Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;

end gate_level;

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