Tuesday, December 15, 2020

VHDL program for implementing the following POS expression using data flow modelling: (~a v~ b) ^ (~a v c) ^ (b v c)

--VHDL program for implementing the following POS expression using data flow modelling:
--(~a v~ b) ^ (~a v c) ^ (b v c)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity product_of_sum6 is
Port
(A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
F : out STD_LOGIC);
end product_of_sum6;
architecture gate_level of product_of_sum6 is
begin
F <= (((NOT A)OR(NOT B))AND((NOT A)OR C)AND(B OR C));
end gate_level;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

VHDL program for implementing the following SOP expression using data flow modelling (a ^ b) v (b ^ ~c) v (c ^ ~a)

--VHDL program for implementing the following SOP expression using data flow modelling:
--(a ^ b) v (b ^ ~c) v (c ^ ~a)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sum_of_product15 is
Port
(A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
F : out STD_LOGIC);
end sum_of_product15;
architecture gate_level of sum_of_product15 is
begin
F <= ((A AND B)OR(B AND (NOT C))OR(C AND (NOT A)));
end gate_level;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

VHDL program for implementing a 8:1 multiplexer using if-else statements.

--VHDL program for implementing a 8 to 1 multiplexer using if-else statements.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplexer8_1_if_else is
     port(
         din : in STD_LOGIC_VECTOR(7 downto 0);
         sel : in STD_LOGIC_VECTOR(2 downto 0);
         dout : out STD_LOGIC
         );
end multiplexer8_1_if_else;
architecture multiplexer8_1_arc of multiplexer8_1_if_else is
begin
    dout <= din(7) when (sel="000") else
            din(6) when (sel="001") else
            din(5) when (sel="010") else
            din(4) when (sel="011") else
            din(3) when (sel="100") else
            din(2) when (sel="101") else
            din(1) when (sel="110") else
            din(0);
end multiplexer8_1_arc;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

VHDL program for implementing a 3:8 decoder using behavioural modelling.

--VHDL program for implementing a 3 to 8 decoder using behavioural modelling.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY decoder_3_8_behav IS
PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END decoder_3_8_behav;
ARCHITECTURE BEHAVIORAL OF decoder_3_8_behav IS
BEGIN
PROCESS(SEL,DIN)
BEGIN
CASE SEL IS
WHEN "000"=>DOUT<="00000001";
WHEN "001"=>DOUT<="00000010";
WHEN "010"=>DOUT<="00000100";
WHEN "011"=>DOUT<="00001000";
WHEN "100"=>DOUT<="00010000";
WHEN "101"=>DOUT<="00100000";
WHEN "110"=>DOUT<="01000000";
WHEN "111"=>DOUT<="10000000";
WHEN OTHERS=>DOUT<="ZZZZZZZZ";
END CASE;
END PROCESS;
END BEHAVIORAL;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

VHDL program for implementing a 1:8 demultiplexer using Case statement.

--VHDL program for implementing a 1 to 8 demultiplexer using Case statement.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demultiplexer1_8_case is
     port(
         din : in STD_LOGIC;
         sel : in STD_LOGIC_VECTOR(2 downto 0);
         dout : out STD_LOGIC_VECTOR(7 downto 0)
         );
end demultiplexer1_8_case;
architecture demultiplexer1_8_arc of demultiplexer1_8_case is
begin
    dout <= (din & "0000000") when (sel="000") else
            ('0' & din & "000000") when (sel="001") else
            ("00" & din & "00000") when (sel="010") else
            ("000" & din & "0000") when (sel="011") else
            ("0000" & din & "000") when (sel="100") else
            ("00000" & din & "00") when (sel="101") else
            ("000000" & din & '0') when (sel="110") else
            ("0000000" & din) ;
end demultiplexer1_8_arc;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

VHDL Code to design an ALU.

--VHDL Code to design an ALU.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
Port ( inp_a : in signed(3 downto 0);
inp_b : in signed(3 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
out_alu : out signed(3 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(inp_a, inp_b, sel)
begin
case sel is
when "000" =>
out_alu<= inp_a + inp_b;
when "001" =>
out_alu<= inp_a - inp_b;
when "010" =>
out_alu<= inp_a - 1;
when "011" =>
out_alu<= inp_a + 1;
when "100" =>
out_alu<= inp_a and inp_b;
when "101" =>
out_alu<= inp_a or inp_b;
when "110" =>
out_alu<= not inp_a ;
when "111" =>
out_alu<= inp_a xor inp_b;
when others =>
NULL;
end case;
end process;
end Behavioral;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

VHDL Code to implement RAM by INTEL.

--VHDL Code to implement RAM by INTEL.

library IEEE;
use IEEE.std_logic_1164.all;
entity ram_intel is
port(
clock : in std_logic;
data : in std_logic_vector(3 downto 0);
write_addr : in integer range 0 to 31;
read_addr : in integer range 0 to 31;
we : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end ram_intel;
architecture rtl of ram_intel is
type mem is array(0 to 31) of std_logic_vector(3 downto 0);
signal ram_block : mem;
begin
process(clock)
begin
if (clock'event and clock='1')then
if(we = '1')then
ram_block(write_addr)<=data;
end if;
q<=ram_block(read_addr);
end if;
end process;
end rtl;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

VHDL Code to implement 128X8 single port RAM.

--VHDL Code to implement 128X8 single port RAM.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity Single_port_RAM_VHDL is
port(
RAM_ADDR: in std_logic_vector(6 downto 0);
RAM_DATA_IN: in std_logic_vector(7 downto 0);
RAM_WR: in std_logic;
RAM_CLOCK: in std_logic;
RAM_DATA_OUT: out std_logic_vector(7 downto 0)
);
end Single_port_RAM_VHDL;
architecture Behavioral of Single_port_RAM_VHDL is
type RAM_ARRAY is array (0 to 127 ) of std_logic_vector (7 downto 0);
signal RAM: RAM_ARRAY :=(
x"55",x"66",x"77",x"67",-- 0x00:
x"99",x"00",x"00",x"11",-- 0x04:
x"00",x"00",x"00",x"00",-- 0x08:
x"00",x"00",x"00",x"00",-- 0x0C:
x"00",x"00",x"00",x"00",-- 0x10:
x"00",x"00",x"00",x"00",-- 0x14:
x"00",x"00",x"00",x"00",-- 0x18:
x"00",x"00",x"00",x"00",-- 0x1C:
x"00",x"00",x"00",x"00",-- 0x20:
x"00",x"00",x"00",x"00",-- 0x24:
x"00",x"00",x"00",x"00",-- 0x28:
x"00",x"00",x"00",x"00",-- 0x2C:
x"00",x"00",x"00",x"00",-- 0x30:
x"00",x"00",x"00",x"00",-- 0x34:
x"00",x"00",x"00",x"00",-- 0x38:
x"00",x"00",x"00",x"00",-- 0x3C:
x"00",x"00",x"00",x"00",-- 0x40:
x"00",x"00",x"00",x"00",-- 0x44:
x"00",x"00",x"00",x"00",-- 0x48:
x"00",x"00",x"00",x"00",-- 0x4C:
x"00",x"00",x"00",x"00",-- 0x50:
x"00",x"00",x"00",x"00",-- 0x54:
x"00",x"00",x"00",x"00",-- 0x58:
x"00",x"00",x"00",x"00",-- 0x5C:
x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00"
);
begin
process(RAM_CLOCK)
begin
if(rising_edge(RAM_CLOCK)) then
if(RAM_WR='1') then
RAM(to_integer(unsigned(RAM_ADDR))) <= RAM_DATA_IN;
end if;
end if;
end process;
RAM_DATA_OUT <= RAM(to_integer(unsigned(RAM_ADDR)));
end Behavioral;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program to create a parity checker circuit in VHDL Modelling.

--Program to create a parity checker circuit in VHDL Modelling.
library IEEE;
use IEEE.std_logic_1164.all;
entity parity_checker is
port ( IE : in std_logic; -- Even input IE active high
IO : in std_logic; -- Odd input IO active high
OE : out std_logic; -- Even output OE active high
OO : out std_logic; -- Odd output OO active high
D : in std_logic_vector(3 downto 0));
end parity_checker;
architecture parity_arch of parity_checker is
signal TEMP : std_logic;
begin
TEMP <= D(0) xor D(1) xor D(2) xor D(3);
OE <= TEMP xor IE;
OO <= TEMP xor IO;
end parity_arch;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program to create a parity generator circuit in VHDL Modelling.

--Program to create a parity generator circuit in VHDL Modelling.

library ieee;
use ieee.std_logic_1164.all;
entity parity_generator is
port (a0, a1, a2, a3: in std_logic; p_odd, p_even: out std_logic);
end parity_generator;
architecture parity of parity_generator is
begin
process (a0, a1, a2, a3)
begin
if (a0 ='0' and a1 ='0' and a2 ='0' and a3 ='0')
then p_odd <= '0';
p_even <= '0';
else
p_odd <= (((a0 xor a1) xor a2) xor a3);
p_even <= not(((a0 xor a1) xor a2) xor a3);
end if;
end process;
end parity;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program to create Full Adder using case statement in VHDL behavioral modelling.

--Program to create Full Adder using case statement in VHDL behavioral modelling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder_case is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
cr : out std_logic);
end full_adder_case;
architecture Behavioral of full_adder_case is
begin
process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
s<='0';
cr<='0';
elsif( a='0' and b='0' and c='1')then
s<='1';
cr<='0';
elsif( a='0' and b='1' and c='0')then
s<='1';
cr<='0';
elsif( a='0' and b='1' and c='1')then
s<='0';
cr<='1';
elsif( a='1' and b='0' and c='0')then
s<='1';
cr<='0';
elsif( a='1' and b='0' and c='1')then
s<='0';
cr<='1';
elsif( a='1' and b='1' and c='0')then
s<='0';
cr<='1';
else
s<='1';
cr<='1';
end if;
end process;
end Behavioral;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program to create Full Subtractor using case statement in VHDL behavioral modelling.

--Program to create Full Subtractor using case statement in VHDL behavioral modelling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_subtractor_case is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : out std_logic;
br : out std_logic);
end full_subtractor_case;
architecture Behavioral of full_subtractor_case is
begin
process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
d<='0';
br<='0';
elsif( a='0' and b='0' and c='1')then
d<='1';
br<='1';
elsif( a='0' and b='1' and c='0')then
d<='1';
br<='1';
elsif( a='0' and b='1' and c='1')then
d<='0';
br<='1';
elsif( a='1' and b='0' and c='0')then
d<='1';
br<='0';
elsif( a='1' and b='0' and c='1')then
d<='0';
br<='0';
elsif( a='1' and b='1' and c='0')then
d<='0';
br<='0';
else
d<='1';
br<='1';
end if;
end process;
end Behavioral;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program for 4:1 Multiplexer using VHDL behavioral modelling.

--Program for 4 to 1 Multiplexer using VHDL behavioral modelling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity behav_MUX_4_1 is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
I : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC);
end behav_MUX_4_1;
architecture Behavioral of behav_MUX_4_1 is
begin
process (S,I)
begin
if (S <= "00") then
Y <= I(0);
elsif (S <= "01") then
Y <= I(1);
elsif (S <= "10") then
Y <= I(2);
else
Y <= I(3);
end if;
end process;
end Behavioral;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program to create Full Subtractor using VHDL behavioral modelling

--Program to create Full Subtractor using VHDL behavioral modelling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_subtractor_behav is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : out std_logic;
di : out std_logic);
end full_subtractor_behav;
architecture Behavioral of full_subtractor_behav is
begin
process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
d<='0';
di<='0';
elsif( a='0' and b='0' and c='1')then
d<='1';
di<='1';
elsif( a='0' and b='1' and c='0')then
d<='1';
di<='1';
elsif( a='0' and b='1' and c='1')then
d<='0';
di<='1';
elsif( a='1' and b='0' and c='0')then
d<='1';
di<='0';
elsif( a='1' and b='0' and c='1')then
d<='0';
di<='0';
elsif( a='1' and b='1' and c='0')then
d<='0';
di<='0';
else
d<='1';
di<='1';
end if;
end process;
end Behavioral;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program to create Full Adder using VHDL behavioral modelling.

--Program to create Full Adder using VHDL behavioral modelling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder_behav is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
cr : out std_logic);
end full_adder_behav;
architecture Behavioral of full_adder_behav is
begin
process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
s<='0';
cr<='0';
elsif( a='0' and b='0' and c='1')then
s<='1';
cr<='0';
elsif( a='0' and b='1' and c='0')then
s<='1';
cr<='0';
elsif( a='0' and b='1' and c='1')then
s<='0';
cr<='1';
elsif( a='1' and b='0' and c='0')then
s<='1';
cr<='0';
elsif( a='1' and b='0' and c='1')then
s<='0';
cr<='1';
elsif( a='1' and b='1' and c='0')then
s<='0';
cr<='1';
else
s<='1';
cr<='1';
end if;
end process;
end Behavioral;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program to create 1:4 Demultiplexer using VHDL.

--Program to create 1 to 4 Demultiplexer using VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demux_1_4 is
port(
din : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end demux_1_4;
architecture demultiplexer_case_arc of demux_1_4 is
begin
demux : process (din,sel) is
begin
case sel is
when "00" => dout <= din & "000";
when "01" => dout <= '0' & din & "00";
when "10" => dout <= "00" & din & '0';
when others => dout <= "000" & din;
end case;
end process demux;
end demultiplexer_case_arc;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program to create 4 bit Magnitude comparator using VHDL.

--Program to create 4 bit Magnitude comparator using VHDL.

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity magnitude_comparator_4_bit is
port (
A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
greater, equal, smaller : out std_logic
);
end magnitude_comparator_4_bit ;
architecture bhv of magnitude_comparator_4_bit is
begin
greater <= '1' when (A > B)
else '0';
equal <= '1' when (A = B)
else '0';
smaller <= '1' when (A < B)
else '0';
end bhv;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

VHDL Program to implement 2:4 Decoder using Case statement.

--VHDL Program to implement 2 to 4 Decoder using Case statement.

library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
entity decoder_case is port( din : in STD_LOGIC_VECTOR(1 downto 0); 
dout : out STD_LOGIC_VECTOR(3 downto 0) ); 
end decoder_case; 
architecture decoder_case_arc of decoder_case is begin decoder : 
process (din) is begin case din is when "00" => dout <= "1000"; 
when "01" => dout <= "0100"; 
when "10" => dout <= "0010"; 
when others => dout <= "0001"; 
end case; 
end process decoder; 
end decoder_case_arc;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program for 8:3 Encoder using VHDL data flow modeling.

--Program for 8 to 3 Encoder using VHDL data flow modeling.

library ieee;
use ieee.std_logic_1164.all;
entity data_flow_encoder_8_3 is
port(i0,i1,i2,i3,i4,i5,i6,i7:in bit; o0,o1,o2: out bit);
end data_flow_encoder_8_3;
architecture dataflow of data_flow_encoder_8_3 is
begin
o0<=i4 or i5 or i6 or i7;
o1<=i2 or i3 or i6 or i7;
o2<=i1 or i3 or i5 or i7;
end dataflow;


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Program for 8:3 Encoder using VHDL behavioral modeling.

--Program for 8 to 3 Encoder using VHDL behavioral modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity behav_encoder_8_3 is
port(
din : in STD_LOGIC_VECTOR(7 downto 0);
dout : out STD_LOGIC_VECTOR(2 downto 0));
end behav_encoder_8_3;
architecture Behavioral of behav_encoder_8_3 is
begin
process(din)
begin
if (din="10000000")then
dout <= "000";
elsif(din="01000000")then
dout <= "001";
elsif(din="00100000")then
dout <= "010";
elsif(din="00010000")then
dout <= "011";
elsif(din="00001000")then
dout <= "100";
elsif(din="00000100")then
dout <= "101";
elsif(din="00000010")then
dout <= "110";
else dout <= "111";
end if;
end process;
end Behavioral;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Program for 8:1 encoder using VHDL behavioral modeling.

--Program for 8 to 1 encoder using VHDL behavioral modeling.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY behav_encoder_8_1 IS
PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DOUT:OUT STD_LOGIC);
END behav_encoder_8_1;
ARCHITECTURE BEHAVIORAL OF behav_encoder_8_1 IS
BEGIN
PROCESS(DIN,SEL)
BEGIN
CASE SEL IS
WHEN"000"=>DOUT<=DIN(0);
WHEN"001"=>DOUT<=DIN(1);
WHEN"010"=>DOUT<=DIN(2);
WHEN"011"=>DOUT<=DIN(3);
WHEN"100"=>DOUT<=DIN(4);
WHEN"101"=>DOUT<=DIN(5);
WHEN"110"=>DOUT<=DIN(6);
WHEN"111"=>DOUT<=DIN(7);
WHEN OTHERS=>
DOUT<='Z';
END CASE;
END PROCESS;
END BEHAVIORAL;


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posted by Saradwata Bandyopadhyay @ December 15, 2020   0 Comments

Sunday, December 13, 2020

Program for 3:8 decoder using VHDL Data flow modeling.

--Program for 3 to 8 decoder using VHDL Data flow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_3_8 is
Port ( S : in STD_LOGIC_VECTOR (2 downto 0);
Q : out STD_LOGIC_VECTOR (7 downto 0));
end decoder_3_8;
architecture dataflow of decoder_3_8 is
begin
Q <="00000001" when S="000" else
    "00000010" when S="001" else
    "00000100" when S="010" else
    "00001000" when S="011" else
    "00010000" when S="100" else
    "00100000" when S="101" else
    "01000000" when S="110" else
    "10000000";
end dataflow;


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posted by Saradwata Bandyopadhyay @ December 13, 2020   0 Comments

Program for 2:4 decoder using VHDL Data flow modeling.

--Program for 2 to 4 decoder using VHDL Data flow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_2_4 is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_2_4;
architecture dataflow of decoder_2_4 is
begin
Q <= "0001" when S="00"
else"0010" when S="01"
else"0100" when S="10"
else"1000" when S="11";
end dataflow;


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posted by Saradwata Bandyopadhyay @ December 13, 2020   0 Comments

VHDL Program to Design a 4 bit parity checker.

--VHDL Program to Design a 4 bit parity checker.

library IEEE;
use IEEE.std_logic_1164.all;
entity parity is
port ( IE : in std_logic; -- Even input IE active high
IO : in std_logic; -- Odd input IO active high
OE : out std_logic; -- Even output OE active high
OO : out std_logic; -- Odd output OO active high
D : in std_logic_vector(3 downto 0));
end entity;
architecture parity_arch of parity is
signal TEMP : std_logic;
begin
TEMP <= D(0) xor D(1) xor D(2) xor D(3);
OE <= TEMP xor IE;
OO <= TEMP xor IO;
end parity_arch;


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posted by Saradwata Bandyopadhyay @ December 13, 2020   0 Comments

VHDL Program to implement Priority Encoder using Case Statement.

--VHDL Program to implement Priority Encoder using Case Statement.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity encoder is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0)
);
end encoder;
architecture bhv of encoder is
begin
process(a)
begin
case a is
when "1000" => b <= "00"; 
when "0100" => b <= "01"; 
when "0010" => b <= "10"; 
when "0001" => b <= "11"; 
when others => b <= "ZZ";
end case;
end process;
end bhv;


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posted by Saradwata Bandyopadhyay @ December 13, 2020   0 Comments

VHDL Program to implement Priority Encoder using If-Else statement.

--VHDL Program to implement Priority Encoder using If-Else statement.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity encoder1 is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0)
);
end encoder1;
architecture bhv of encoder1 is
begin
process(a)
begin
if (a="1000") then
b <= "00";
elsif (a="0100") then
b <= "01";
elsif (a="0010") then
b <= "10";
elsif (a="0001") then
b <= "11";
else
b <= "ZZ";
end if;
end process;
end bhv;


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posted by Saradwata Bandyopadhyay @ December 13, 2020   0 Comments

VHDL Program to implement 2:4 Decoder using If-Else statement.

--VHDL Program to implement 2 to 4 Decoder using If-Else statement.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder1 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder1;
architecture bhv of decoder1 is
begin
process(a)
begin
if (a="00") then
b <= "0001";
elsif (a="01") then
b <= "0010";
elsif (a="10") then
b <= "0100";
else
b <= "1000";
end if;
end process;
end bhv;


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posted by Saradwata Bandyopadhyay @ December 13, 2020   0 Comments

Saturday, December 12, 2020

VHDL Program to implement 1:4 DeMultiplexer using Case statement.

--VHDL Program to implement 1 to 4 DeMultiplexer using Case statement.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demultiplexer_case is
port(
din : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end demultiplexer_case;
architecture demultiplexer_case_arc of demultiplexer_case is
begin
demux : process (din,sel) is
begin
case sel is
when "00" => dout <= din & "000";
when "01" => dout <= '0' & din & "00";
when "10" => dout <= "00" & din & '0';
when others => dout <= "000" & din;
end case;
end process demux;
end demultiplexer_case_arc;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL Program to implement 1:4 DeMultiplexer using If-Else statement.

--VHDL Program to implement 1 to 4 DeMultiplexer using If-Else statement.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demultiplexer1_4 is
port(
din : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC_VECTOR (3 downto 0)
);
end demultiplexer1_4;
architecture demultiplexer1_4_arc of demultiplexer1_4 is
begin
demux : process (din,sel) is
begin
if (sel="00") then
dout <= din & "000";
elsif (sel="01") then
dout <= '0' & din & "00";
elsif (sel="10") then
dout <= "00" & din & '0';
else
dout <= "000" & din;
end if;
end process demux;
end demultiplexer1_4_arc;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL Program to implement 4:1 Multiplexer using Case statement.

--VHDL Program to implement 4 to 1 Multiplexer using Case statement.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX4_1 is
port(i:in STD_LOGIC_VECTOR(3 downto 0);
s:in STD_LOGIC_VECTOR(1 downto 0);
y: out STD_LOGIC);
end MUX4_1;
architecture dataflow of MUX4_1 is
begin
with s select
y<= i(0) when"00",
i(1) when"11",
i(2) when"10",
i(3) when others;
end dataflow;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL Program to implement 4:1 Multiplexer using If-Else statement

--VHDL Program to implement 4 to 1 Multiplexer using If-Else statement

library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
entity multiplexer_4_1 is port( din : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0); 
dout : out STD_LOGIC ); 
end multiplexer_4_1; 
architecture multiplexer4_1_arc of multiplexer_4_1 is begin mux : 
process (din,sel) is begin if (sel="00") then dout <= din(3); 
elsif (sel="01") then dout <= din(2); 
elsif (sel="10") then dout <= din(1); 
else dout <= din(0); 
end if; 
end process mux;
end multiplexer4_1_arc;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement 2:1 Multiplexer using data flow modeling.

--VHDL program to implement 2 to 1 Multiplexer using data flow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BASIC_MUX is
port( I0, I1 ,X: in std_logic;
F : out std_logic);
end entity;
architecture dataflow of BASIC_MUX is
begin
F <= ((I0 and (not X)) or (I1 and X));
end dataflow;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement Full Subtractor using data flow modeling.

--VHDL program to implement Full Subtractor using data flow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_sub is
port( A, B, C : in std_logic;
DIFF, Borrow : out std_logic);
end entity;
architecture dataflow of full_sub is
begin
DIFF <= (A xor B) xor C;
Borrow <= ((not A) and (B or C)) or (B and C);
end dataflow;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement Half Subtractor using data flow modeling.

--VHDL program to implement Half Subtractor using data flow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half_sub is
port( A, B : in std_logic;
DIFF, Borrow : out std_logic);
end entity;
architecture dataflow of half_sub is
begin
DIFF <= A xor B;
Borrow <= (not A) and B;
end architecture;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement Full Adder using data flow modeling.

--VHDL program to implement Full Adder using data flow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder_vhdl_code is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end full_adder_vhdl_code;
architecture gate_level of full_adder_vhdl_code is
begin
S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
end gate_level;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement Half Adder using data flow modeling.

--VHDL program to implement Half Adder using data flow modeling.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity half_adder is
port (
i_bit1 : in std_logic;
i_bit2 : in std_logic;
--
o_sum : out std_logic;
o_carry : out std_logic
);
end half_adder;
architecture rtl of half_adder is
begin
o_sum <= i_bit1 xor i_bit2;
o_carry <= i_bit1 and i_bit2;
end rtl;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement any Boolean expression of POS for using VHDL data flow modeling

--VHDL program to implement any Boolean expression of POS for using VHDL data flow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity product_of_sum is
Port
(A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
F : out STD_LOGIC);
end product_of_sum;
architecture gate_level of product_of_sum is
begin
F <= ((A OR B OR C)AND((NOT A)OR B OR C )AND((NOT A)OR(NOT B) OR C)AND((NOT A)OR(NOT B)OR(NOT C)));
end gate_level;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement any Boolean expression of SOP form using VHDL data flow modeling.

--VHDL program to implement any Boolean expression of SOP form using VHDL data flow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sum_of_product is
Port
(A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
F : out STD_LOGIC);
end sum_of_product;
architecture gate_level of sum_of_product is
begin
F <= (((NOT A) AND (NOT B) AND (C )) OR ((NOT A) AND (B) AND (NOT C)) OR ((NOT A) AND B AND C) OR(A AND (NOT B) AND C));
end gate_level;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement XNOR gate using data flow modeling.

--VHDL program to implement XNOR gate using data flow modeling.

library IEEE;
use IEEE.std_logic_1164.all;
entity xnor_gate is
port(
I1 : in std_logic;
I2 : in std_logic;
OA : out std_logic);
end entity xnor_gate;
architecture behav of xnor_gate is
begin
OA <= I1 xnor I2;
end architecture behav;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement XOR gate using data flow modeling.

--VHDL program to implement XOR gate using data flow modeling.

library IEEE;
use IEEE.std_logic_1164.all;
entity xor_gate is
port(
I1 : in std_logic;
I2 : in std_logic;
OA : out std_logic);
end entity xor_gate;
architecture behav of xor_gate is
begin
OA <= I1 xor I2;
end architecture behav;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement NOR gate using data flow modeling.

--VHDL program to implement NOR gate using data flow modeling.

library IEEE;
use IEEE.std_logic_1164.all;
entity nor_gate is
port(
I1 : in std_logic;
I2 : in std_logic;
OA : out std_logic);
end entity nor_gate;
architecture behav of nor_gate is
begin
OA <= I1 nor I2;
end architecture behav;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement NAND gate using data flow modeling.

--VHDL program to implement NAND gate using data flow modeling.

library IEEE;
use IEEE.std_logic_1164.all;
entity nand_gate is
port(
I1 : in std_logic;
I2 : in std_logic;
OA : out std_logic);
end entity nand_gate;
architecture behav of nand_gate is
begin
OA <= I1 nand I2;
end architecture behav;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement AND gate using data flow modeling.

--VHDL program to implement AND gate using data flow modeling.

library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port(I1 : in std_logic;
I2 : in std_logic;
OA : out std_logic);
end entity and_gate;
architecture behav of and_gate is
begin
OA <= I1 and I2;
end architecture behav;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement NOT gate using data flow modeling.

--VHDL program to implement NOT gate using data flow modeling.

library IEEE;
use IEEE.std_logic_1164.all;
entity not_gate is
port(
I1 : in std_logic;
OA : out std_logic);
end entity not_gate;
architecture behav of not_gate is
begin
OA <= not I1;
end architecture behav;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments

VHDL program to implement OR gate using data flow modeling.

--VHDL program to implement OR gate using data flow modeling.

library IEEE;
use IEEE.std_logic_1164.all;
entity or_gate is
port(
I1 : in std_logic;
I2 : in std_logic;
OA : out std_logic);
end entity or_gate;
architecture behav of or_gate is
begin
OA <= I1 or I2;
end architecture behav;


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posted by Saradwata Bandyopadhyay @ December 12, 2020   0 Comments